Flip-flops and latches are well-known non-volatile circuit elements commonly used in electronic integrated circuits. Flip-flops and latches may be used for data storage, or more specifically, storage of state in sequential logic. For example, in the hardware design of finite-state machines (FSMs), pipelined architecture, etc., an output and next state of a flip-flop/latch may be made to depend not only on its current input, but also on its current state (and thereby, on previous inputs). In this manner, sequential flow of control and data can be implemented. For example, with regard to a pipelined processor, flip-flops may be used for the traversal of data through one pipeline stage to the next, based on a corresponding clock signal. In this regard, it is required to be able to write data from a current pipeline stage to the flop-flops as the clock transitions to a next pipeline stage, while being able to read stored data in the flip-flops for the next pipeline stage.
Magnetoresistive Random Access Memory (MRAM) is a non-volatile memory technology that is finding popular applications in many state of the art electronic integrated circuit designs, particularly for its benefits in non-volatile memory systems. While flip-flops and latches based on MRAM technology exhibit several advantages over previously utilized semiconductor devices, the MRAM based flip-flops and latches are also limited in several aspects.
MRAM technology features response (read/write) times comparable to volatile memory, and in contrast to conventional RAM technologies which store data as electric charges or current flows, MRAM uses magnetic elements. The magnetic elements are typically known as magnetic tunnel junction storage elements or “MTJs,” and are formed from two magnetic layers each of which can hold a magnetic field, separated by an insulating (tunnel barrier) layer. One of the two layers (fixed layer), is set to a particular polarity. The polarity of the other layer (free layer) is free to change to match that of an external field that can be applied. A change in the polarity of the free layer will change the resistance of the MTJ. For example, when the polarities are aligned, a low resistance state exists (parallel “P” magnetization low resistance state “0”). When the polarities are not aligned, a high resistance state exists (anti-parallel “AP” magnetization high resistance state “1”). The resistance inside any particular MTJ can be determined by measuring the electrical resistance, for example, by passing a current through the MTJ, and thus determining the resulting resistance state/logic value.
A modification from conventional MRAM is seen in spin transfer torque (STT)-MRAM, or STT-MTJ, where an STT-MTJ uses electrons that become spin-polarized as the electrons pass through a thin film (spin filter). During the write operation, the spin-polarized electrons exert a torque on the free layer, which can switch the polarity of the free layer. The read operation is similar to conventional MRAM in that a current is used to detect the resistance/logic state of the MTJ storage element, as discussed in the foregoing. Read/write circuitry related to an STT-MRAM bit cell (or STT-MTJ) formed in an STT-MRAM array, may include an access transistor coupled to the MTJ, bit lines, source lines, word lines, sense amplifiers, reference voltages, etc., as is known in the art.
In general, the design and construction of read/write circuitry related to the STT-MTJ requires that the same path be utilized for both reading and writing STT-MTJ bit cells, because, STT-MTJs are two-terminal devices. In other words, a separate path for reading an STT-MTJ and a separate path for writing the STT-MTJ are not available. This leads to advantages in terms of improved density of STT-MRAM arrays.
However, the two-terminal device configurations with the same read and write paths are not beneficial for the formation of flip-flops and latches using STT-MTJ bit cells. Since separate read and write paths do not exist, an STT-MTJ bit cell cannot be written while a read operation is being performed on the same STT-MTJ bit cell. Accordingly, it is not possible to construct a flip-flop directly from STT-MTJ bit cells. To achieve the functionality of a flip-flop using STT-MTJ bit cells, requires the construction of two latch stages, a master latch, and a slave latch, as are known in the art. STT-MTJ flip-flops constructed from two-stage latches utilize a large number of additional logic elements, and therefore, fail to harness the advantages of STT-MRAM technology.
For example, with reference to FIG. 1A, a schematic block diagram of a Master-Slave (MS) flip-flop 100 constructed using STT-MTJ bit cells is provided, along with a corresponding circuit diagram of flip-flop 100 in FIG. 1B. The illustrated MS latch design operates similar to a conventional set-reset (SR) latch design, and utilizes a current latch sense amplifier (CLSA). Briefly, with reference to FIG. 1A, the operation involves writing a D input to the master latch during a first clock phase, storing the value in the STT-MTJ and reading out the stored value from the slave latch during a second clock phase. With reference to FIG. 1B. The operation of flip-flop 100 involves storing a data value from the “D” input, as “Q” in the cross coupled latch formed using the MTJs labeled “J” and “Jb.” The data value stored is read out from the “Q” output. In more detail, with continuing reference to FIG. 1B, signals “p1” and “p2” are derived from a system clock “CLK.” The signals p1 and p2 drive the PMOS and NMOS transistors in transistor circuits T1 and T2 as shown, within the master latch. During a first phase of CLK, when p1 is high, input D is stored to the cross-coupled MTJ legs comprising the MTJs J and Jb. One of the terminals (source or drain) of the MTJs J and Jb is connected to a sense amplifier comprising cross-coupled inverters, with output nodes NQ and NQb. The node NQ is produces the output Q after being passed through additional drivers such as inverters. The other terminal (drain or source) of the MTJs J and Jb is connected to each other at node NC and to output nodes NW and NWb0 of cross-coupled inverters comprising transistors M5, M5′, M6, M6′ and M7. The data value stored can be read out from the slave latch from the NQ output (connected to Q) by activating the sense amplifier through the pass transistors coupled to the signal p2 when p2 is high.
Thus, the above design of flip-flop 100 requires a sense amplifier, and equalization of the two MTJ legs comprising MTJs J and Jb. Flip-flop 100 avoids multiple clocks by deriving signals p1 and p2 from the same clock, such that clock routing complexity and overhead are reduced. However, flip-flop 100 suffers from problems in writing to the MTJ cells in the slave latch during a read operation. This is because the sense amplifier needs to be activated for a read operation, which requires bit lines connected to the MTJ legs to be active. On the other hand, the bit lines connected to the MTJ legs need to be floated during a write operation, which provides for conflicting requirements. Therefore, this conventional design for flip-flop 100 is not suitable for forming efficient flip-flops.
With reference to FIGS. 2A-B, another non-volatile flip-flop design based on STT-MTJ cells is illustrated for flip-flop 200. FIG. 2A illustrates a circuit schematic of flip-flop 200 comprising a bridge between a master D-flip-flop (DFF) and a MTJ slave structure. The details of flip-flop 200 are explained further with reference to FIG. 2B which illustrates a detailed circuit diagram. Flip-flop 200 utilizes a voltage divider, rather than the CLSA arrangement of flip-flop 100 above. More specifically, at node n1, a midpoint voltage is derived when MTJ0 and MTJ1 are programmed as follows. When MTJ0 is in a high resistance state (logic “1”) and MTJ1 is in a low resistance state (logic “0”), then the voltage at node n1 is logic “0”. On the other hand, for the opposite combination stored, i.e., MTJ0 in low resistance state (logic “0”) and MTJ1 in high resistance state (logic “1”), midpoint voltage VDD/2 appears at node n1. This midpoint voltage at node n1 is used to control the value D_in input to master DFF, which eventually appears as the node Q, as output D_out. Further detailed operation of flip-flop 200 will be understood by persons skilled in the art. For the sake of this disclosure, it will be recognized that the two MTJs, MTJ0 and MTJ1 cannot be read and written at the same time, and therefore, the additional latches L1 and L2 are required at the master DFF circuit. Since the MTJs are themselves storage devices, the use of additional metal oxide semiconductor (MOS) transistor based storage devices in the master DFF, for example, leads to undesired overhead. Further, flip-flop 200 also requires a two-level latch arrangement, since the MTJs cannot be written during a read operation. For the sake of low power and low cost, it is desirable to have a single stage operation which avoids the complexities and drawbacks of flip-flops 100 and 200 above.